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NCP1607 Cost Effective Power Factor Controller
The NCP1607 is an active power factor controller specifically designed for use as a pre-converter in ac-dc adapters, electronic ballasts, and other medium power off line converters (typically up to 250 W). It utilizes Critical Conduction Mode (CRM) to ensure unity power factor across a wide range of input voltages and power levels. The NCP1607 minimizes the number of external components. The integration of comprehensive safety protection features makes it an excellent choice for designing robust PFC stages. It is available in a SOIC-8 package.
General Features
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1 SO-8 D SUFFIX CASE 751 A L Y W G 8 1607B ALYW G
8
* * * * * * * * * * * * * * *
"Unity" Power Factor No Need for Input Voltage Sensing Latching PWM for Cycle by Cycle On Time Control (Voltage Mode) High Precision Voltage Reference (1.6% over the Temperature Range) Very Low Startup Current Consumption ( 40 mA) Low Typical Operating Current (2.1 mA) Source 500 mA / Sink 800 mA Totem Pole Gate Driver Undervoltage Lockout with Hysteresis Pin to Pin Compatible with Industry Standards This is a Pb-Free Device This Device uses Halogen-Free Molding Compound Programmable Overvoltage Protection Open Feedback Loop Protection Accurate and Programmable On Time Control Accurate Overcurrent Detector
1
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTION
FB Control Ct CS (Top View) VCC DRV GND ZCD
Safety Features
ORDERING INFORMATION
Device NCP1607BDR2G Package SOIC-8 (Pb-Free) Shipping 2500 / Tape & Reel
Typical Applications
* AC-DC Adapters, TVs, Monitors * Off Line Appliances Requiring Power Factor Correction * Electronic Light Ballast
LBOOST
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
DBOOST RZCD + CIN ROUT1 CCOMP ROUT2 CT 1 2 3 4 NCP1607
FB VCC Control DRV Ct CS GND ZCD
VOUT LOAD (Ballast, SMPS, etc.) + CBULK
VCC 8 7 6 5 RS
AC Line
EMI Filter
Figure 1. Typical Application
(c) Semiconductor Components Industries, LLC, 2009
April, 2009 - Rev. 1
1
Publication Order Number: NCP1607/D
NCP1607
VCC Shutdown POK - + VUVP (Enable EA) Dynamic OVP Isink>Iovp IEAsink VDD Enable VEAL Clamp VEAH Clamp VDD CT CT ICHARGE Add VEAL Offset POK PWM - + Static OVP Static OVP is triggered when clamp is activated. Measure Fault uVDD UVP + - + UVLO
VOUT
VCC VDD VDDGD VDD Reg
CBULK
ROUT1 FB ROUT2
RFB
CCOMP Control AC IN LBOOST
VCONTROL
ESD
ESD
RS VDD VCL(NEG) Active Clamp ZCD + RZCD VCL(POS) Clamp +
VSDL uVDD
+
CS
ESD
+
+
DBOOST
ESD
+
E/A - + VREF
DRV LEB + - OCP
SQ RQ VCC Demag UVLO SQ RQ VDDGD SQ RQ SQ RQ POK uVDD GND DRV
VCS(limit) + -
SQ RQ Off Timer Reset
VZCDH + - - + VZCDL
Shutdown
*All SR Latches are Reset Dominant
Figure 2. Block Diagram
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PIN FUNCTION DESCRIPTION
Pin 1 Name FB Function The FB pin is the inverting input of the internal error amplifier. An external resistor divider scales the output voltage to the internal reference voltage to maintain regulation. The feedback information is also used for the programmable overvoltage and undervoltage protections. The controller is disabled when this pin is below the undervoltage protection threshold, VUVP, typically 0.3 V. The Control pin is the output of the internal error amplifier. A compensation network is placed between the Control and FB pins to set the loop bandwidth. A low enough bandwidth is needed to obtain a high power factor ratio and a low THD. The Ct pin sources a current to charge an external timing capacitor. The circuit controls the power switch on time by comparing the Ct voltage to an internal voltage derived from the regulation block. The Ct pin discharges the external timing capacitor at the end of the switching cycle. The CS pin limits the cycle-by-cycle current through the power switch. When the CS voltage exceeds the internal threshold, the MOSFET driver turns off. The sense resistor that connects to the CS pin programs the maximum switch current. The voltage of an auxiliary winding is applied to this pin to detect when the inductor is demagnetized for critical conduction mode operation. The controller is disabled when this pin is grounded. Analog ground. Integrated MOSFET driver capable of driving a high gate charge power MOSFET. The VCC pin is the positive supply of the controller. The controller is enabled when VCC exceeds VCC(on) and remains enabled until VCC decreases below VCC(off).
2 3
Control Ct
4
CS
5 6 7 8
ZCD GND DRV VCC
MAXIMUM RATINGS
Rating Supply Voltage Supply Current DRV Voltage DRV Sink Current DRV Source Current FB Voltage FB Current Control Voltage Control Current Ct Voltage Ct Current CS Voltage CS Current ZCD Voltage ZCD Current Power Dissipation and Thermal Characteristics D suffix, Plastic Package, Case 751 Maximum Power Dissipation @ TA = 70C Thermal Resistance Junction-to-Air Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 s) Symbol VCC ICC VDRV IDRV(sink) IDRV(source) VFB IFB VCONTROL ICONTROL VCt ICt VCS ICS VZCD IZCD Value -0.3 to 20 20 -0.3 to 20 800 500 -0.3 to 10 10 -0.3 to 10 -2 to 10 -0.3 to 6 10 -0.3 to 6 10 -0.3 to 10 10 Unit V mA V mA mA V mA V mA V mA V mA V mA
PD(SO) RqJA(SO) TJ TJ(MAX) TSTG TL
450 178 -40 to 125 150 -65 to 150 300
mW C/W C C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pins 1-6, 8: Human Body Model 2000 V per JEDEC Standard JESD22-A114E, Machine Model Method 200 V per JEDEC Standard JESD22-A115-A Pin 7: Human Body Model 2000 V per JEDEC Standard JESD22-A114E, Machine Model Method 180 V per JEDEC Standard JESD22-A115-A 2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1607
ELECTRICAL CHARACTERISTICS
(For typical values, TJ = 25C. For min/max values, TJ = -40C to +125C, unless otherwise specified, VCC = 12 V, VFB = 2.4 V, VCS = 0 V, VCONTROL = open, VZCD = open, CDRV = 1 nF, CT = 1 nF) Characteristics VCC UNDERVOLTAGE LOCKOUT SECTION VCC Startup Threshold (Undervoltage Lockout Threshold, Vcc rising) -25C < TJ < +125C -40C < TJ < +125C VCC Disable Voltage after Turn On (Undervoltage Lockout Threshold, VCC falling) -25C < TJ < +125C -40C < TJ < +125C Undervoltage Lockout Hysteresis DEVICE CONSUMPTION ICC consumption during startup: 0 V < VCC < VCC(on) - 200 mV ICC consumption after turn on at No Load, 70 kHz switching ICC consumption after turn on at 70 kHz switching ICC consumption after turn on at no switching (such as during OVP fault, UVP fault, or grounding ZCD) REGULATION BLOCK (ERROR AMPLIFIER) Voltage Reference TJ = 25 C -25C < TJ < +125C -40C < TJ < +125C VREF 2.475 2.465 2.460 -2.0 8.0 -2.0 - - 0.25 2.0 -1.0 4.9 1.85 3.0 0.45 150 40 -1.0 1.9 1.45 300 -2.0 5.0 5.0 0.45 2.50 2.50 2.50 - 17 -6.0 80 1.0 0.53 4.7 - 5.3 2.1 3.2 0.5 256 100 - 2.1 1.6 500 - 5.7 8.5 0.6 2.525 2.535 2.540 2.0 - - - - 1.25 10 1.0 5.7 2.4 3.4 0.55 350 170 1.0 2.3 1.75 800 +2.0 6.5 - 0.75 V ICC(startup) ICC1 ICC2 ICC(fault) - - - - 23.5 1.4 2.17 1.2 40 2.0 3.0 1.6 mA mA mA mA VCC(on) 11.0 10.9 8.7 8.5 2.2 11.8 11.8 9.5 9.5 2.5 13.0 13.1 10.3 10.5 2.8 V Symbol Min Typ Max Unit
VCC(off)
V
HUVLO
V
VREF Line Regulation from VCC(on) + 200 mV < VCC < 20 V, TJ = 25C Error Amplifier Current Capability: (Note 3) Sink (VControl = 4 V, VFB = 2.6 V): Source (VControl = 4 V, VFB = 2.4 V): Error Amplifier Open Loop DC Gain (Note 4) Unity Gain Bandwidth (Note 4) FB Bias Current (VFB = 2.5 V) FB Pull Down Resistor (VFB = 2.5 V) Control Pin Bias Current (FB = 0 V and VCONTROL = 4.0 V) VCONTROL (IEASOURCE = 0.5 mA, VFB = 2.4 V) VCONTROL (IEASINK = 0.5 mA, VFB = 2.6 V) VEA(diff) = VEAH - VEAL CURRENT SENSE BLOCK Overcurrent Voltage Threshold Leading Edge Blanking Duration Overcurrent Voltage Propagation Delay CS Bias Current (VCS = 2 V) ZERO CURRENT DETECTION Zero Current Detection Threshold (VZCD rising) Zero Current Detection Threshold (VZCD falling) VZCDH - VZCDL Maximum ZCD bias Current (VZCD = 5 V) Upper Clamp Voltage (IZCD = 2.5 mA) Current Capability of the Positive Clamp at VZCD = VCL(POS) + 200 mV: Negative Active Clamp Voltage (IZCD = -2.5 mA) 3. Parameter values are valid for transient conditions only. 4. Parameter characterized and guaranteed by design, but not tested in production.
VREF(line) IEA
mV mA
GOL BW IFB RFB ICONTROL VEAH VEAL VEA(diff) VCS(limit) tLEB tCS ICS VZCDH VZCDL VZCD(HYS) IZCD VCL(POS) ICL(POS) VCL(NEG)
dB MHz mA MW mA V V V V ns ns mA V V mV mA V mA V
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ELECTRICAL CHARACTERISTICS
(For typical values, TJ = 25C. For min/max values, TJ = -40C to +125C, unless otherwise specified, VCC = 12 V, VFB = 2.4 V, VCS = 0 V, VCONTROL = open, VZCD = open, CDRV = 1 nF, CT = 1 nF) Characteristics Current Capability of the Negative Active Clamp: in normal mode (VZCD = 300 mV) in shutdown mode (VZCD = 100 mV) Shutdown Threshold (VZCD falling) Enable Threshold (VZCD rising) Shutdown Comparator Hysteresis Zero Current Detection Propagation Delay Minimum Detectable ZCD Pulse Width Drive off Restart Timer RAMP CONTROL Ct Charge Current (VCT = 0 V) -25C < TJ < +125C -40C < TJ < +125C ICHARGE tCT(discharge) VCTMAX tPWM IOVP 243 235 - 2.9 2.9 - 270 270 - 3.2 3.2 142 297 297 100 3.3 3.4 220 mA ns V ns mA Symbol ICL(NEG) 2.5 35 VSDL VSDH VSD(HYS) tZCD tSYNC tSTART 150 - - - - 75 3.7 70 205 290 85 100 70 179 5.0 100 250 350 - 170 - 300 mA mA mV mV mV ns ns ms Min Typ Max Unit
Time to discharge a 1 nF Ct capacitor from VCT = 3.4 V to 100 mV. Maximum Ct level before DRV switches off PWM Propagation Delay OVER AND UNDERVOLTAGE PROTECTION Dynamic Overvoltage Protection (OVP) Triggering Current: TJ = 25C TJ = -40C to +125C Hysteresis of the dynamic OVP current before the OVP latch is released Static OVP Threshold Voltage Undervoltage Protection (UVP) Threshold Voltage GATE DRIVE SECTION Gate Drive Resistance: ROH @ ISOURCE = 100 mA ROL @ ISINK = 100 mA Drive voltage rise time from 10% VCC to 90% VCC Drive voltage fall time from 90% VCC to 10% VCC Driver output voltage at VCC = VCC(on) - 200 mV and Isink = 10 mA 3. Parameter values are valid for transient conditions only. 4. Parameter characterized and guaranteed by design, but not tested in production. -25C < TJ < +125C -40C < TJ < +125C
9.0 8.7 - - 0.25
10.5 - 8.5 VEAL + 100 mV 0.302
11.8 12.1 - - 0.4
IOVP(HYS) VOVP VUVP
mA V V W
ROH ROL trise tfall VOUT(start)
- - - - -
12 6.0 30 25 -
18 10 80 70 0.2
ns ns V
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TYPICAL CHARACTERISTICS
ICHARGE, Ct CHARGE CURRENT (mA) 274 272 ton, ON TIME (ms) 270 268 266 264 262 260 -50 -25 0 25 50 75 100 125 150 14 12 Ct = 1 nF 10 8 6 4 2 0 0 1 2 3 VCONTROL (V) 4 5 6
TEMPERATURE (C)
Figure 3. Ct Charge Current vs. Temperature
3.30 VCTMAX, MAXIMUM Ct LEVEL (V) 3.25 3.20 3.15 3.10 3.05 3.00 -50 170
Figure 4. On Time vs. VCONTROL Level
tPWM, PWM PROPAGATION DELAY (ns)
160
150
140
-25
0
25
50
75
100
125
150
130 -50
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 5. Maximum Ct Level vs. Temperature
2.505 VREF, REFERENCE VOLTAGE (V) 2.500 2.495 2.490 2.485 2.480 2.475 2.470 -50 -25 0 25 50 75 100 125 100 GOL, OPEN LOOP GAIN (dB) 80
Figure 6. PWM Propagation Delay vs. Temperature
200 160 GAIN 60 PHASE 40 20 0 120 80 40 0 -40 10M PHASE ()
150
-20 10
100
1k
10k
100k
1M
TEMPERATURE (C)
FREQUENCY (Hz)
Figure 7. Reference Voltage vs. Temperature
Figure 8. Error Amplifier Open Loop Gain and Phase
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TYPICAL CHARACTERISTICS
12 IOVP, DYNAMIC OVP TRIGGERING CURRENT (mA) RFB, FEEDBACK RESISTOR (MW) 100 125 150 11 IOVP 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150
10 9 8 7 -50
IOVP(HYS)
-25
0
25
50
75
TEMPERATURE (C)
TEMPERATURE (C)
Figure 9. Dynamic OVP Triggering Current vs. Temperature
ICC2, SWITCHING SUPPLY CURRENT (mA) ICC(startup), STARTUP CURRENT (mA) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 -50 26 24 22 20 18 16
Figure 10. Feedback Resistor vs. Temperature
-25
0
25
50
75
100
125
150
14 -50
-25
0
25
50
75
100
125 150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. Switching Supply Current vs. Temperature
VCC, SUPPLY VOLTAGE THRESHOLD (V) 13 12 11 10 9 8 -50 tSTART, RESTART TIMER (ms) VCC(on) 200
Figure 12. Startup Current vs. Temperature
190
180
VCC(off)
170
-25
0
25
50
75
100
125
150
160 -50
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. Supply Voltage Thresholds vs. Temperature
Figure 14. Restart Timer vs. Temperature
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TYPICAL CHARACTERISTICS
ROH/OL, GATE DRIVE RESISTANCE (W) 18 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 240 -50 -25 0 25 50 75 100 125 150 tLEB, LEB DURATION (ns) ISOURCE = 100 mA ROH ISINK = 100 mA ROL 280
270
260
250
TEMPERATURE (C)
TEMPERATURE (C)
VCS(limit), OVERCURRENT THRESHOLD VOLTAGE (V)
Figure 15. Gate Drive Resistance vs. Temperature
VUVP, UVP THRESHOLD VOLTAGE (V) 0.520 0.515 0.510 0.505 0.500 0.495 0.490 0.485 0.480 -50 -25 0 25 50 75 100 125 0.320 0.315 0.310 0.305 0.300 0.295 0.290 0.285 0.280 -50
Figure 16. LEB Duration vs. Temperature
150
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 17. Overcurrent Threshold Voltage vs. Temperature
VSDH/SDL, SHUTDOWN THRESHOLD (V) 0.35
Figure 18. Undervoltage Protection Threshold Voltage vs. Temperature
0.30
VSDH
0.25 VSDL
0.20
0.15 -50
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 19. Shutdown Thresholds vs. Temperature
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NCP1607
Introduction
The NCP1607 is a voltage mode power factor correction (PFC) controller designed to drive cost effective pre-converters to meet input line harmonic regulations. This controller operates in critical conduction mode (CRM) for optimal performance in applications up to 250 W. Its voltage mode scheme enables it to obtain unity power factor without the need for a line sensing network. The output voltage is accurately controlled by a high precision error amplifier. The controller also implements a comprehensive array of safety features for robust designs. The key features of the NCP1607 are as follows: * Constant on time (Voltage Mode) CRM operation. High power factor ratios are easily obtained without the need for input voltage sensing. This allows for optimal standby power consumption. * Accurate and Programmable On Time Limitation. The NCP1607 uses an accurate current source and an external capacitor to generate the on time. * High Precision Voltage Reference. The error amplifier reference voltage is guaranteed at 2.5 V 1.6% over process, temperature, and voltage supply levels. This results in very accurate output voltages. * Very Low Startup Current Consumption. The circuit consumption is reduced to a minimum (< 40 mA) during the startup phase, allowing fast, low loss, charging of VCC. The architecture of the NCP1607 gives a controlled undervoltage lockout level and provides ample VCC hysteresis during startup. * Powerful Output Driver. A Source 500 mA / Sink 800 mA totem pole gate driver is used to provide rapid turn on and turn off times. This allows for improved efficiencies and the ability to drive higher power MOSFETs. Additionally, a combination of active and passive circuitry is used to ensure that the driver output voltage does not float high while VCC is below its turn on level. * Programmable Overvoltage Protection (OVP). The adjustable OVP feature protects the PFC stage against excessive output overshoots that could damage the application. These events can typically occur during the startup phase or when the load is abruptly removed. * Protection against Open Feedback Loop (Undervoltage Protection). Undervoltage protection (UVP) disables the PFC stage when the output voltage is excessively low. This also protects the circuit in case of a failure in the feedback network: if no voltage is applied to FB because of a poor connection or if the FB pin is floating, UVP is activated shutting down the converter. * Overcurrent Limitation. The peak current is accurately limited on a pulse by pulse basis. The level is adjustable by modifying the current sense resistor. An
*
integrated LEB filter reduces the chance of noise prematurely triggering the overcurrent limit. Shutdown Features. The PFC pre-converter is placed in a shutdown mode by grounding the FB pin or the ZCD pin. During this mode, the ICC current consumption is reduced and the error amplifier is disabled.
Application information
Most electronic ballasts and switching power supplies use a diode bridge rectifier and a bulk storage capacitor to produce a dc voltage from the utility ac line (Figure 20). This DC voltage is then processed by additional circuitry to drive the desired output.
Rectifiers AC Line + Bulk Storage Capacitor Converter
Load
Figure 20. Typical Circuit without PFC
This simple rectifying circuit draws power from the line when the instantaneous ac voltage exceeds the capacitor voltage. Since this occurs near the line voltage peak, the resulting current draw is non sinusoidal and contains a very high harmonic content. This results in a poor power factor (typically < 0.6) and consequently, the apparent input power is much higher than the real power delivered to the load. Additionally, if multiple devices are tied to the same input line, the effect is magnified and a "line sag" effect can be produced (see Figure 21).
Vpk Rectified DC 0 AC Line Voltage 0 AC Line Current
Line Sag
Figure 21. Typical Line Waveforms without PFC
Increasingly, government regulations and utility requirements necessitate control over the line current harmonic content. To meet this need, power factor correction is implemented with either a passive or active circuit. Passive circuits usually contain a combination of large capacitors, inductors, and rectifiers that operate at the ac line frequency. Active circuits incorporate some form of a high frequency switching converter that regulates the
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input current to stay in phase with the input voltage. These circuits operate at a higher frequency and so they are smaller, lighter in weight, and more efficient than a passive circuit. With proper control of an active PFC stage, almost any complex load can be made to appear in phase with the ac line, thus significantly reducing the harmonic current
Rectifiers
content. Because of these advantages, active PFC circuits have become the most popular way to meet harmonic content requirements. Generally, they consist of inserting a PFC pre-regulator between the rectifier bridge and the bulk capacitor (Figure 22).
Converter
PFC Preconverter
AC Line
+
High Frequency Bypass Capacitor
+ NCP1607
Bulk Storage Capacitor
Load
Figure 22. Active PFC Pre-Converter with the NCP1607
The boost (or step up) converter is the most popular topology for active power factor correction. With the proper control, it produces a constant voltage while drawing a sinusoidal current from the line. For medium power (<300 W) applications, critical conduction mode (also called borderline conduction mode) is the preferred control method. Critical conduction mode (CRM) occurs at the boundary between discontinuous conduction mode
Diode Bridge + IN - VIN + L Vdrain IN IL
(DCM) and continuous conduction mode (CCM). In CRM, the next driver on time is initiated when the boost inductor current reaches zero. CRM operation is an ideal choice for medium power PFC boost stages because it combines the lower peak currents of CCM operation with the zero current switching of DCM operation. The operation and waveforms in a PFC boost converter are illustrated in Figure 23.
Diode Bridge + VIN + L Vdrain + VOUT IL
-
The power switch is ON With the power switch voltage being about zero, the input voltage is applied across the coil. The coil current linearly increases with a (VIN/L) slope. Coil Current VIN/L IL(pk)
The power switch is OFF The coil current flows through the diode. The coil voltage is (VOUT - VIN) and the coil current linearly decays with a (VOUT - VIN)/L slope. (VOUT - VIN)/L Critical Conduction Mode: Next current cycle starts as soon as the core is reset.
Vdrain
VOUT VIN If next cycle does not start then Vdrain rings towards VIN
Figure 23. Schematic and Waveforms of an Ideal CRM Boost Converter
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When the switch is closed, the inductor current increases linearly to its peak value. When the switch opens, the inductor current linearly decreases to zero. At this point, the drain voltage of the switch (Vd) is essentially floating and begins to drop. If the next switching cycle does not start, then the voltage will ring with a dampened frequency around Vin. A simple derivation of equations (such as found in AND8123), leads to the result that good power factor correction in CRM operation is achieved when the on time is constant across an ac cycle and is equal to:
ton + 2 @ P OUT @ L h @ Vac 2
(eq. 1) VIN(pk) IL(pk) VIN(t) IL(t)
IIN(pk)
IIN(t)
MOSFET
ON OFF
A simple plot of this switching over an ac line cycle is illustrated in Figure 24. The off time varies based on the instantaneous line voltage, but the on time is kept constant. This naturally causes the peak inductor current (IL(pk)) to follow the ac line voltage. The NCP1607 represents an ideal method to implement this constant on time CRM control in a cost effective and robust solution. The device incorporates an accurate regulation circuit, a low power startup circuit, and advanced protection features.
VOUT ROUT1 FB RFB ROUT2 CCOMP VCONTROL Control +
Figure 24. Inductor Waveform During CRM Operation ERROR AMPLIFIER REGULATION
The NCP1607 is configured to regulate the boost output voltage based on its built in error amplifier (EA). The error amplifier 's negative terminal is pinned out to FB, the positive terminal is tied to a 2.5 V 1.6% reference, and the output is pinned out to Control (Figure 25).
EA - + VREF ton(MAX)
PWM BLOCK
Slope +
Ct I CHARGE
ton
tPWM VEAL VCONTROL VEAH
Figure 25. Error Amplifier and On Time Regulation Circuits
A resistor divider from the boost output to the input of the EA sets the FB level. If the output voltage is too low, then the FB level will drop and the EA will cause the control voltage to increase. This increases the on time of the driver, which increases the power delivered and brings the output back into regulation. Alternatively, if the output voltage (and hence FB voltage) is too high, then the control level decreases and the driver on times are shortened. In this way, the circuit regulates the output voltage (VOUT) so that the VOUT portion that is applied to FB through the resistor
divider ROUT1 and ROUT2 is equal to the internal reference (2.5 V). The output voltage is set using Equation 2:
VOUT + V REF @ R OUT1 ) R EQ R EQ
(eq. 2)
Where REQ is the parallel combination of ROUT2 and RFB. REQ is calculated using Equation 3:
REQ + R OUT2 @ R FB R OUT2 ) R FB
(eq. 3)
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NCP1607
A compensation network is placed between the FB and Control pins to reduce the speed at which the EA responds to changes in the boost output. This is necessary due to the nature of an active PFC circuit. The PFC stage absorbs a sinusoidal current from a sinusoidal line voltage. Hence, the converter provides the load with a power that matches the average demand only. Therefore, the output capacitor must "absorb" the difference between the delivered power and the power consumed by the load. This means that when the power fed to the load is lower than the demand, the output capacitor discharges to compensate for the lack of power. Alternatively, when the supplied power is higher than that absorbed by the load, the output capacitor charges to store the excess energy. The situation is depicted in Figure 26.
Iac Vac PIN POUT
VOUT
Figure 26. Output Voltage Ripple for a Constant Output Power
As a consequence, the output voltage exhibits a ripple at a frequency of either 100 Hz (for 50 Hz mains such as in Europe) or 120 Hz (for 60 Hz mains in the USA). This ripple must not be taken into account by the regulation loop because the error amplifier's output voltage must be kept constant over a given ac line cycle for a proper shaping of the line current. Due to this constraint, the regulation bandwidth is typically set below 20 Hz. For a simple type 1 compensation network, only a capacitor is placed between FB and Control (see Figure 1). In this configuration, the capacitor necessary to attenuate the bulk voltage ripple is given by:
10 20 CCOMP + 4 @ p fline @ ROUT1
G
Control
VCONTROL
VDD ICHARGE Ct DRV VCt VCt(off) VEAL + PWM - +
ton
VCONTROL - VEAL
(eq. 4)
where G is the attenuation level in dB (commonly 60 dB)
ON TIME SEQUENCE
ton DRV
Since the NCP1607 is designed to control a CRM boost converter, its switching pattern must accommodate constant on times and variable off times. The Controller generates the on time via an external capacitor connected to pin 3 (Ct). A current source charges this capacitor to a level determined by the Control pin voltage. Specifically, Ct is charged to VCONTROL minus the VEAL offset (2.1 V typical). Once this level is exceeded, the drive is turned off (Figure 27).
Figure 27. On Time Generation
Since VCONTROL varies with the RMS line level and output load, this naturally satisfies equation 1. And if the values of compensation components are sufficient to filter
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NCP1607
out the bulk voltage ripple, then this on time is truly constant over the ac line cycle. Note that the maximum on time of the controller occurs when VCONTROL is at its maximum. Therefore, the Ct capacitor must be sized to ensure that the required on time can be delivered at full power and the lowest input voltage condition. The maximum on time is given by:
ton(MAX) + Ct @ VCTMAX I CHARGE
(eq. 5) DRV
VOUT Drain
VZCD(off)
Combining this equation with equation 1, gives:
Ct w 2 @ P OUT @ L @ I CHARGE h @ Vac 2 @ V CTMAX
(eq. 6) VZCD(on) VCL(POS) VZCDH VZCDL VCL(NEG) Winding
where VCTMAX = 2.9 V (min) ICHARGE = 297 mA (max)
OFF TIME SEQUENCE
ZCD
While the on time is constant across the ac cycle, the off time in CRM operation varies with the instantaneous input voltage. The NCP1607 determines the correct off time by sensing the inductor voltage. When the inductor current drops to zero, the drain voltage ("Vdrain" in Figure 23) is essentially floating and naturally begins to drop. If the switch is turned on at this moment, then CRM operation will be achieved. To measure this high voltage directly on the inductor is generally not economical or practical. Rather, a smaller winding is taken off of the boost inductor. This winding, called the zero current detector (ZCD) winding, gives a scaled version of the inductor output and is more useful to the controller.
NB NZCD
Figure 28. Voltage Waveforms for Zero Current Detection
Figure 28 gives typical operating waveforms with the ZCD winding. When the drive is on, a negative voltage appears on the ZCD winding. And when the drive is off, a positive voltage appears. When the inductor current drops to zero, then the ZCD voltage falls and starts to ring around zero volts. The NCP1607 detects this falling edge and starts the next driver on time. To ensure that a ZCD event has truly occurred, the NCP1607's logic (Figure 29) waits for the ZCD pin voltage to rise above VZCDH (2.1 V typical) and then fall below VZCDL (1.6 V typical). In this way, CRM operation is easily achieved.
Vin
+ - VDD RSENSE ZCD + RZCD VCL(POS) Clamp VCL(NEG) Active Clamp + - + VSDL 13 + VZCDH + - VZCDL DRIVE
Q Reset Dominant Latch R Q
S
Demag
Shutdown
Figure 29. Implementation of the ZCD Winding
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NCP1607
To prevent negative voltages on the ZCD pin, the pin is internally clamped to VCL(NEG) (600 mV typical) when the ZCD winding is negative. Similarly, the ZCD pin is clamped to VCL(POS) (5.7 V typical), when the voltage rises too high. Because of these clamps, a resistor (RZCD in Figure 29) is necessary to limit the current from the ZCD winding to the ZCD pin. At startup, there is no energy in the ZCD winding and therefore no voltage signal to activate the ZCD comparators. This means that the driver could never turn on. Therefore, to enable the PFC stage to startup under these conditions, an internal watchdog timer is integrated into the controller. This timer turns the drive on if the driver has been off for more than 180 ms (typical). This feature is deactivated during a fault mode (OVP, UVP, or Shutdown), and reactivated when the fault is removed.
STARTUP
level, the internal references and logic of the NCP1607 turn on. The controller has an undervoltage lockout (UVLO) feature which keeps the part active until VCC drops below VCC(off) (9.5 V typical). This hysteresis allows ample time for the auxiliary winding to take over and supply the necessary power to VCC (Figure 30).
VCC(on) VCC(off)
VCC
Figure 30. Typical VCC Startup Waveform
Generally, a resistor connected between the ac input and VCC (pin 8) charges the VCC capacitor to the VCC(on) level (12 V typical). Because of the very low consumption of the NCP1607 during this stage (< 40 mA), most of the current goes directly to charging up the VCC capacitor. This provides faster startup times and reduced standby power dissipation. When the VCC voltage exceeds the VCC(on)
DBOOST +
When the PFC pre-converter is loaded by a switch mode power supply (SMPS), then it is often preferable to have the SMPS controller startup first. The SMPS can then supply the NCP1607 VCC directly. Advanced controllers, such as the NCP1230 or NCP1381, can control when to turn on the PFC stage (see Figure 31) leading to optimal system performance. This setup also eliminates the startup resistors and therefore improves the no load power dissipation of the system.
CBULK 1 2 3 4 NCP1607 8 7 6 5 PFC_VCC + 1 2 3 4 NCP1230 8 7 6 5 VCC + + +
Figure 31. NCP1607 Supplied by a Downstream SMPS Controller (NCP1230) QUICK START and SOFT START
At startup, the error amplifier is enabled and Control is pulled up to VEAL (2.1 V typical). This is the lowest level of control voltage which produces output drives. This feature, called "quick start," eliminates the delay at startup
associated with charging the compensation network to its minimum level. This also produces a natural "soft-start" mode where the controller's power ramps up from zero to the required power (see Figure 32).
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NCP1607
VCC(on) VCC(off)
OUTPUT DRIVER
VCC
IM VREF
The NCP1607 includes a powerful output driver capable of peak currents of Source 500 mA / Sink 800 mA. This enables the controller to efficiently drive power MOSFETs for medium power (up to 300 W) applications. Additionally, the driver stage is equipped with both passive and active pull down clamps (Figure 33). The clamps are active when VCC is off and force the driver output to well below the threshold voltage of a power MOSFET.
FB
Control VEAL Natural Soft Start
VOUT
Figure 32. Startup Timing Diagram Showing the Natural Soft Start of the Control Pin
VCC
+ - +
UVLO
VDD VDDGD VDDREG
UVLO DRV IN
DRV
uVDD
GND
Figure 33. Output Driver Stage and Pull Down Clamps Overvoltage Protection
The low bandwidth of the feedback network makes active PFC stages very slow systems. One consequence of this is the risk of huge overshoots in abrupt transient phases (startup, load steps, etc.). For reliable operation, it is critical that some form of overvoltage protection (OVP) effectively prevents the output voltage from rising too high. The NCP1607 detects these excessive VOUT levels
and disables the driver until the output voltage returns to nominal levels. This keeps the output voltage within an acceptable range. The limit is adjustable so that the overvoltage level can be optimally set. The level must not be so low that it is triggered by the 100 or 120 Hz ripple of the output voltage, but it must be low enough so as not to require a larger voltage rating of the output capacitor. Figure 34 depicts the operation of the OVP circuitry.
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NCP1607
VOUT + IRFB FB E/A - + RFB CCOMP Enable VCONTROL Control ICONTROL VEAH Clamp + VREF Measure ICONTROL VDD VEAL Static OVP Clamp Static OVP is triggered when clamp is activated. (Enable EA) Dynamic OVP ICONTROL > Iovp Fault IROUT1 ROUT1 - + VUVP UVP
IROUT2 ROUT2
Figure 34. OVP and UVP Circuit Blocks
When the output voltage is in steady state equilibrium, ROUT1 and ROUT2 regulate the FB voltage to VREF. During this equilibrium state, no current flows through the compensation capacitor (CCOMP shown in Figure 34). These facts allow the following equations to be derived: * The ROUT1 current is:
V * V REF IROUT1 + OUT R OUT1
(eq. 7)
IROUT1 +
V OUT(OVP) * V REF ROUT1
+
V OUT ) DVOUT * VREF ROUT1
(eq. 11)
* The error amplifier sinks:
IControl + I ROUT1 * I EQ +
where DVOUT is the output voltage excess.
V OUT ) DVOUT * VREF ROUT1 VREF REQ
*
* The REQ current is:
IEQ + V REF R EQ + I ROUT2 ) I FB
(eq. 8)
(eq. 12)
The combination of Equations 2 and 12 yield a simple expression of the current sunk by the error amplifier:
ICONTROL + DV OUT R OUT1
* And since no current flows through CCOMP,
IROUT1 + V OUT * V REF R OUT1 * V REF R EQ
(eq. 9)
Under stable conditions, Equations 7 through 9 are true. Conversely, when VOUT is not at the target voltage, the output of the error amplifier sinks or sources the current necessary to maintain VREF on pin 1. In the case of an overvoltage condition: * The error amplifier maintains VREF on pin 1, and the REQ current remains the same as the steady state value:
IEQ + V REF R EQ
(eq. 10)
The current absorbed by pin 2 (IControl) is proportional to the output voltage excess. The circuit senses this current and disables the drive (pin 7) when IControl exceeds IOVP (10.4 mA typical). The OVP threshold is calculated using Equation 13.
VOUT(OVP) + V OUT ) R OUT1 @ I OVP
(eq. 13)
The OVP limit is set by adjusting ROUT1. ROUT1 is calculated using Equation 14.
ROUT1 + V OUT(OVP) * V OUT IOVP
(eq. 14)
* The ROUT1 current is increased and is calculated using
Equation 11:
For example, if 440 V is the maximum output voltage and 400 V is the target output voltage, then ROUT1 is calculated using Equation 14.
ROUT1 + 440 * 400 + 3.846 MW 10.4m
If ROUT1 is selected as 4 MW,, then VOUT(OVP) = 442 V.
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NCP1607
STATIC OVERVOLTAGE PROTECTION
If the OVP condition lasts for a long time, it may happen that the error amplifier output reaches its minimum level (i.e. Control = VEAL). It would then not be able to sink any current and maintain the OVP fault. Therefore, to avoid any discontinuity in the OVP disabling effect, the circuit incorporates a comparator which detects when the lower level of the error amplifier is reached. This event, called "static OVP", disables the output drives. Once the OVP event is over, and the output voltage has dropped to normal, then Control rises above the lower limit and the driver is re-enabled (Figure 35).
VOUT
However, if the FB pin voltage increases and exceeds the UVP level, then the controller will start the application up normally.
VCC(on) VCC(off) VCC
VOUT VOUT FB 2.5 V VUVP VEAH Control UVP Fault is "Removed"
DRV
VEAL UVP Wait
UVP Wait
VEAH VEAL IOVPH IOVPL
VCONTROL
UVP
ICONTROL Dynamic OVP
Figure 36. The NCP1607's Startup Sequence with and without a UVP Fault
The voltage on the output which exits a UVP fault is given by:
VOUT(UVP) + R OUT1 ) R EQ @ V UVP R EQ
(eq. 15)
Static OVP
Figure 35. OVP Timing Diagram NCP1607 Undervoltage Protection (UVP)
If ROUT1 = 4 MW and REQ = 25.16 kW, then the VOUT UVP threshold is 48 V. This corresponds to an input voltage of approximately 34 Vac.
Open Feedback Loop Protection
When the PFC stage is plugged in, the output voltage is forced to roughly equate the peak line voltage. The NCP1607 detects an undervoltage fault when this output voltage is unusually low, such that the feedback voltage is below VUVP (300 mV typical). In an UVP fault, the drive output and error amplifier (EA) are disabled. The latter is done so that the EA does not source a current which would increase the FB voltage and prevent the UVP event from being accurately detected. The UVP feature helps to protect the application if something is wrong with the power path to the bulk capacitor (i.e. the capacitor cannot charge up) or if the controller cannot sense the bulk voltage (i.e. the feedback loop is open). Furthermore, the NCP1607 incorporates a novel startup sequence which ensures that undervoltage conditions are always detected at startup. It accomplishes this by waiting approximately 180 ms after VCC reaches VCC(on) before enabling the error amplifier (Figure 36). During this wait time, it looks to see if the feedback (FB) voltage is greater than the UVP threshold. If not, then the controller enters a UVP fault and leaves the error amplifier disabled.
The NCP1607 features comprehensive protection against open feedback loop conditions by including OVP, UVP, and Floating Pin Protection (FPP). Figure 37 illustrates three conditions in which the feedback loop is open. The corresponding number below describes each condition shown in Figure 37. 1. UVP Protection: The connection from resistor ROUT1 to the FB pin is open. ROUT2 pulls down the FB pin to ground. The UVP comparator detects a UVP fault and the drive is disabled. 2. OVP Protection: The connection from resistor ROUT2 to the FB pin is open. ROUT1 pulls up the FB pin to the output voltage. The ESD diode clamps the FB voltage to 10 V and ROUT1 limits the current into the FB pin. The VEAL clamp detects a static OVP fault and the drive is disabled. 3. FPP Protection: The FB pin is floating. The internal pulldown resistor RFB pulls down the FB voltage below the UVP threshold. The UVP comparator detects a UVP fault and the drive is disabled.
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NCP1607
UVP and OVP protect the system from low bulk voltages and rapid operating point changes respectively, while the FPP protects the system against floating feedback pin conditions. If FPP is not implemented and a manufacturing error causes the feedback pin to float, then the feedback voltage is dependent on the coupling within the system and the surrounding environment. The coupled feedback voltage may be within the regulation limits (i.e. above the UVP threshold, but below VREF) and cause the controller to deliver excessive power. The result is that the output voltage rises until a component fails due to the voltage stress. The tradeoff for including FPP is that the value of RFB causes an error in the output voltage. The output voltage including the error caused by RFB (VOUT) is calculated using Equation 16:
VOUT + V OUT ) R OUT1 @ V REF RFB
(eq. 16)
The error caused by RFB is compensated by adjusting ROUT2. The parallel combination of RFB and ROUT2 form an equivalent resistor REQ that is calculated using Equation 17.
REQ + R OUT1 @ REQ + 4 M @ V REF V OUT * V REF
(eq. 17)
2.5 + 25.16 kW 400 * 2.5
REQ is used to calculate ROUT2.
ROUT2 + ROUT2 + R EQ @ R FB R FB * R EQ 25.16 k @ 4.7 M 4.7 M * 25.16 k + 25.29 kW
(eq. 18)
The compensated output voltage is calculated using Equation 19.
VOUT + VREF @ ROUT1 ) ROUT2 R OUT2 4 M ) 25.29 k 25.29 k ) ROUT1 @ )4 M@ VREF RFB (eq. 19)
Using the values from the OVP calculation, the output voltage including the error caused by RFB is equal to:
VOUT + 400 ) 4 M @ 2.5 4.7 M + 402 V
VOUT + 2.5 @
2.5 4.7 M
+ 400 V
VOUT ROUT1 Condition 1 Condition 3 FB Condition 2 ROUT2 CCOMP RFB + +
+ VUVP E/A + VREF
UVP
(Enable EA) Dynamic OVP Measure VDD VEAL Static OVP Clamp Static OVP is triggered when clamp is activated VEAH Clamp ICONTROL > Iovp Fault
ICONTROL
Enable VCONTROL Control ICONTROL
Figure 37. Open Feedback Loop Protection Overcurrent Protection (OCP)
A dedicated pin on the NCP1607 senses the peak current and limits the driver on time if this current exceeds VCS(limit). This level is 0.5 V (typical). Therefore, the maximum peak current can be adjusted by changing RSENSE according to:
Ipeak + V CS(limit) RS
(eq. 20)
An internal LEB filter (Figure 38) reduces the likelihood of switching noise falsely triggering the OCP limit. This filter blanks out the first 250 ns (typical) of the current sense signal. If additional filtering is necessary, a small RC filter can be added between RSENSE and the CS pin.
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NCP1607
SHUTDOWN MODE
DRV CS LEB + RS optional VOUT ROUT1 NCP1607 CCOMP 1 2 3 Shutdown ROUT2 4
FB VCC
+ - VCS(limit)
OCP
Figure 38. OCP Circuitry with Optional External RC Filter
The NCP1607 allows for two methods to place the controller into a standby mode of operation. The FB pin can be pulled below the UVP level (300 mV typical) or the ZCD pin can be pulled below the VSDL level (200 mV typical). If the FB pin is used for shutdown (Figure 39(a)), care must be taken to ensure that no significant leakage current exists on the shutdown circuitry. This could impact the output voltage regulation. If the ZCD pin is used for shutdown (Figure 39(b)), then any parasitic capacitance created by the shutdown circuitry will add to the delay in detecting the zero inductor current event.
LBOOST
NCP1607 8 7 6 5 1 2 3 4
FB VCC
8 7 6 5
RZCD
Control DRV Ct CS GND ZCD
Control DRV Ct CS GND ZCD
Shutdown
Figure 39(a)
Figure 39(b)
Figure 39. Shutting Down the PFC Stage by Pulling FB to GND (A) or Pulling ZCD to GND (B)
To activate the shutdown feature on ZCD, the internal clamp must first be overcome. This clamp will draw a maximum of ICL(NEG) (5.0 mA maximum) before releasing and allowing the ZCD pin voltage to drop low enough to shutdown the part (Figure 40). After shutdown, the
5 mA
comparator includes approximately 90 mV of hysteresis to ensure noise free operation. A small current source (70 mA typical) is also activated to pull the unit out of the shutdown condition when the external pull down is released.
~70 mA Controller Disabled
IZCD Shutdown
Controller Enabled VSDL VSDH VCL(NEG) ~1 V
Figure 40. Shutdown Comparator and Current Draw to Overcome Negative Clamp
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NCP1607
Application Information
ON Semiconductor provides an electronic design tool, a demonstration board and an application note to facilitate the design of the NCP1607 and reduce development cycle time. All the tools can be downloaded or ordered at www.onsemi.com.
The electronic design tool allows the user to easily determine most of the system parameters of a boost pre-converter. The demonstration board is a boost pre-converter that delivers 100 W at 400 V. The circuit schematic is shown in Figure 41. The pre-converter design is described in Application Note AND8353/D.
RSTART1 LBOOST RSTART2 DBOOST
NTC J3
t
BRIDGE F1 L1 R1 C3 D1
RCTUP1
L2
DAUX RZCD
C2
CVCC
+
DVCC
RO1A RO1B
J2 C1
RCTUP2 CIN
J1
CCOMP CCOMP1RCOMP2
1 2 3 4
U1 NCP1607 FB Ct CS VCC
8 7 6 5
CBUL
K
+
CVCC DDRV
2
Control DRV GND ZCD
RDRV
Q1
RCT CT2 CT1
ROUT2B RS3 RS2 RS1
ROUT2A
RCS CCS CZCD
Figure 41. Application Board Circuit Schematic
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NCP1607
BOOST DESIGN EQUATIONS Components are identified in Figure 1
RMS Input Current
Iac +
Maximum Inductor Peak Current Inductor Value
POUT h @ Vac 2 @ 2 @ P OUT h @ Vac LL
V OUT 2
h (the efficiency of only the Boost PFC stage) is generally in the range of 90 - 95% Where VacLL is the minimum line input voltage. Ipk(MAX) occurs at the lowest line voltage. fSW(MIN) is the minimum desired switching frequency. The maximum L must be calculated at low line and high line. The maximum on time occurs at the lowest line voltage and maximum output power. The off time is greatest at the peak of the ac line voltage and approaches zero at the ac line zero crossings. Theta (q) represents the angle of the ac line voltage.
Ipk(MAX) +
2 @ Vac 2 @ Lv
* Vac
VOUT @ Vac @ I pk(MAX) @ fSW(min) ton(MAX) + 2 @ L @ P OUT h @ Vac LL 2 ton
V OUT Vac@ sin(q) @ 2 *1
Maximum On Time
Off Time
toff +
Frequency
fSW +
Pin 3 Capacitor
Vac 2 @ h @ 2 @ L @ P OUT Ct w
1*
Vac @ |sin q| @ 2 V OUT
ICHARGE and VCTMAX are given in the NCP1607 specification table. Where VacHL is the maximum line input voltage. The turns ratio must be low enough so as to trigger the ZCD comparators at high line. RZCD must be large enough so that the shutdown comparator is not inadvertently activated.
2 @ P OUT @ L @ I CHARGE h @ Vac 2 @ V CTMAX
Boost Turns to ZCD Turns Ratio
V * Vac HL @ 2 NB : N ZCD v OUT V ZCDH RZCD w Vac HL @ 2 I CL(NEG) @ (N B : N ZCD) R OUT1 ) R EQ R EQ
Resistor from ZCD winding to the ZCD pin (pin 5) Boost Output Voltage
VOUT + V REF @ REQ +
R OUT2 @ R FB R OUT2 ) R FB V OUT(OVP) * V OUT IOVP V REF
IOVP is given in the NCP1607 specification table.
Maximum VOUT voltage prior to OVP activation and the necessary ROUT1 and ROUT2.
VOUT(OVP) + V OUT ) I OVP @ R OUT1 ROUT1 +
REQ + R OUT1 @ ROUT2 +
Minimum output voltage necessary to exit undervoltage protection (UVP) Bulk Cap Ripple
V OUT * V REF
R EQ ) R FB R FB * R EQ R OUT1 ) R EQ R EQ
VUVP is given in the NCP1607 specification table. Use fline = 47 Hz for worst case at universal lines. The ripple must not exceed the OVP level for VOUT.
VOUT(UVP) + V UVP @ Vripple(pk-pk) +
POUT C BULK @ 2 @ p @ fline @ VOUT 2 @ P OUT 3 @ Vac LL @ h 2@ 2 p@ P OUT h @ Vac LL @ VOUT
Inductor RMS Current
IL(RMS) + ID(RMS)MAX + 4 @ 3
Boost Diode RMS Current
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NCP1607
BOOST DESIGN EQUATIONS Components are identified in Figure 1
MOSFET RMS Current
Pout IM(RMS)MAX + 2 @ @ 3 h @ Vac LL RS + V CS(limit) I pk(MAX)
1*
8 @ 2 @ Vac LL 3 p @ V out
VCS(limit) is given in the NCP1607 specification table.
MOSFET Sense Resistor
PRS + I M(RMS) 2 @ RS
Bulk Capacitor RMS Current Type 1 CCOMP
IC(RMS) +
32 @ 2 @ P OUT 2 * (ILOAD(RMS)) 2 9 @ p @ Vac LL @ VOUT @ h2 CCOMP + 10 G 20 4 @ p @ f line @ ROUT1
G is the desired attenuation in decibels (dB). Typically it is 60 dB.
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NCP1607
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
-X- A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
The product described herein (NCP1607), may be covered by the following U.S. patents: 5,073,850 and 6,362,067. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative
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NCP1607/D

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